This invention relates generally to integrated circuit memories, and, more particularly, to a bootstrapped word line decoder circuit for providing voltages at or above a full VDD potential to a word line load.
This application is related to a copending application assigned to the assignee of the present application entitled "Bootstrapping Circuit Utilizing a Ferroelectric Capacitor", Ser. No. 08/620,799, filed on Mar. 28, 1996, which is hereby incorporated by reference.
There are many bootstrapping circuits in existence, which are generally known to include capacitive coupling for the purpose of increasing the voltage on a gate of an NMOS transistor so that one source/drain node of the NMOS transistor can deliver the full voltage on the other source/drain node, usually a VDD power supply voltage. Some prior art bootstrapping circuits rely on a large chargestorage element to supply the necessary charge during the bootstrapping operation. These circuits therefore do not lend themselves to being used in "pitched" circuitry, which is necessary for a compact layout configuration. Another problem in prior art bootstrapping circuits is that they become inoperable under low power supply voltage conditions, i.e. power supply voltages less than or equal to 3.3 volts. This is especially true for situations wherein the threshold voltage, V.sub.TH, of the MOS transistors used becomes equal to 50% of the operating power supply voltage VDD.
Turning now to FIG. 1, a portion of a typical memory architecture 10 is shown. Memory architecture 10 includes an address buffer 16 for receiving a control signal designated CNTRL SIG on line 12 and an external address bus designated EXT ADD on bus 14. Address buffer 16 generates internal address signals designated INT ADD on bus 18, which is received by an address decoder 20. Address decoder 20 generates decoded word line address signals designated AI, AJ, and AK, on lines 22, 24, and 26, respectively. The decoded word line address signals are received by multiple word line decoders, one for every row of memory cells in memory array 44. Four representative word line decoders 28, 30, 32, and 34 are shown in FIG. 1, designated WL DECODER 1, WL DECODER 2, WL DECODER N-1, and WL DECODER N, respectively. The outputs of the word line decoders are designated WL1, WL2, WLN-1, and WLN on word lines 36, 38, 40, and 42, respectively. Word lines 36-42 are coupled to a memory array 44. The rows and columns of memory cells in memory array 44 are not shown. Two control signals designated CTL and WLCLK are generated by a control and timing logic block 46. The CTL signal is a control signal on line 50, and the WLCLK signal is a clock signal on line 52.
Turning now to FIG. 2, the schematic diagram for a typical prior art word line decoder 28 is shown. Word line decoder 28 is suitable for in-pitch layout, but has low voltage performance problems as is further described below. Address signals AI, AJ, and AK are received at nodes 22, 24, and 26 by a three-input NAND gate 60. The output of NAND gate 60 is coupled to one input of a two-input NOR gate 62. The other input of NOR gate 62 receives the CTL control signal at node 50. The output of NOR gate 62 is coupled to a source/drain (current node) of transistor 66 through line 64. The signal on line 64 is designated WLEN. The gate (control node) of transistor 66 is coupled to the VDD power supply voltage. The other source/drain of transistor 66 is coupled to the gate of transistor 70 through line 68. The signal on line 68 is designated WL'. One source/drain of transistor 70 receives the WLCLK signal at node 52 and the other source/drain of transistor 70 is the output of word line decoder 28 coupled to a word line at node 36.
In operation, a word line is selected when all three address signals are high. Some time after the word line is selected the CTL signal is activated, which isolates transistor 66. Some time after the CTL signal is activated, the WLCLK signal is activated, which bootstraps the WL' voltage to a voltage greater than the VDD power supply voltage, assuring that the full pulsed value of the WLCLK signal (the VDD power supply voltage, typically five volts) appears at the output on node 36.
While the prior art word line decoder described above will provide the full VDD power supply voltage to the selected word line when a five volt power supply is used, performance becomes compromised when the power supply voltage is dropped to 3.3 volts or less. At these low voltages, which can actually be specified to as low as about 2.5 volts, the body-affected threshold voltage, V.sub.TH, of the transistors used in the design can become a significant portion of the available voltage. When V.sub.TH is about 50% of VDD, word line decoder 28 becomes inoperable. Since the gate of transistor 66 is coupled to VDD, the voltage WL' on line 68 will be VDD--V.sub.TH, which is approximately equal to V.sub.TH under low voltage conditions. Since the output at node 36 is also required to be driven above ground (preferably to VDD volts), there is no voltage to turn on transistor 70 and word line decoder 28 becomes inoperable.
What is desired, therefore, is a word line decoder that maintains the useful qualities of the prior art word line decoder circuit described above, such as all N-channel transistors in the main signal path, and an in-pitch layout configuration, but that is able to operate at very low VDD voltage conditions less than or equal to 3.3 volts.